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02 / Chiplet

ChipletContract Development

Design, assembly and manufacturing of chiplets (heterogeneous bonding), including compound semiconductors. Not limited to sensors, we take on full custom development to customer specifications.

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02 / Chiplet

ChipletContract Development

Design, assembly and manufacturing of chiplets (heterogeneous bonding), including compound semiconductors. Not limited to sensors, we take on full custom development to customer specifications.

2D simulation of electric field strength and direction in a PD device pixel cross-section (created for web publication)
PRODUCT · 01

PD Device Design & Prototyping

  • MaterialsSi / CdTe / TlBr, etc.
  • ScopeDesign and prototyping of detector elements (PD devices)
  • StatusBy individual consultation
View details →
Hierarchical diagram zooming in from the full chip to blocks and down to the circuit elements of a single pixel (created for web publication)
PRODUCT · 02

ASIC Design & Prototyping

  • StructureHybrid structure (TSV-based)
  • ScopeDesign and prototyping of readout integrated circuits (ASICs)
  • StatusBy individual consultation
View details →
Stacked cross-section of a 3D-CMOS showing the X-ray entrance surface, scintillator, silicon substrate, insulating layer, photodiode, RDL, microbumps and readout ASIC
PRODUCT · 03

CoW Assembly / Multi-Layer Stacking

  • Assembly methodChip on Wafer (CoW) / multi-layer stacking
  • BondLow-temperature, low-pressure bonding with bumps of 20μmΦ or less
  • StatusBy individual consultation
View details →
SERVICES

Development Flow

ANSeeN handles design and overall integration, outsourcing wafer fabrication, 3D processing, stacking and tiling to multiple manufacturing partners (common to CdTe and 3D-CMOS). From consultation to mass production, we proceed while reviewing deliverables at each phase.

Development flow common to CdTe and 3D-CMOS. ANSeeN designs the circuits, wafer map and PD; an LSI design house creates the layout and GDS; a foundry fabricates and die-sorts the ASIC wafers; a 3D assembly manufacturer performs TSV, RDL, stacking and dicing; an assembly manufacturer tiles onto patterned substrates and inspects; and ANSeeN performs final assembly
  • ProcessConsultation → Specification → Design → Prototyping → Evaluation → Mass production
  • Design & developmentDesign of PD devices and ASICs, including heterogeneous bonding of compound semiconductors with CMOS
  • Assembly & manufacturingAssembly and supply from prototyping through mass production

→ See the business story (Applications)

PROCESS

Bonding & Assembly Process

Heterogeneous bonding makes two different types of semiconductor, a detector element and an ASIC, function as a single sensor. Our own Imaging products (CdTe PhotonCounting FPD and 3D CMOS FPD) serve as direct proof of this technology.

01 / PROCESS

Build separately

Comparison of monolithic fabrication and heterogeneous chiplets

Semiconductors with different materials and processes cannot be made on a single wafer. The detector element that converts X-rays into charge (CdTe, Si, etc.) and the CMOS logic that reads out the signal are each optimized and made separately, then bonded at low temperature and low pressure using bumps of 20μmΦ or less. The bonded chips are tiled to achieve large areas impossible on a single wafer.

  • Actual scale
    Photo of a chiplet on a fingertipPhoto of a die with a detector element bonded to an ASIC
    A chiplet small enough to sit on a fingertip is the basic unit of this business.
02 / PROCESS

Stack Only Known-Good Dies

Structural diagram of Chip on Wafer (CoW) and multi-layer stacking

Low-temperature, low-pressure bonding with bumps of 20μmΦ or less preserves the properties of delicate compound semiconductors.

  • CoW (Chip on Wafer)Good chips selected by die sorting are bonded onto a target wafer, so defective dies are never stacked together.
  • Multi-layer stackingDetector elements, ASICs and interposers are connected with TSV and RDL and stacked vertically.
  • Bumps
    Cross-sectional SEM image of an Ag paste bump jointMicrograph of a bump array
    Plated μbumps (Sn/Ag) and printed conductive paste (Ag). Paste enables stacking at room temperature.
  • TilingStacked chips are arranged with small gaps on a Si interposer or PCB to achieve large areas.
03 / PROCESS

Case Study: CdTe

CdTe FPD manufacturing process diagram (from ASIC wafer to panel testing)
  • ASIC waferThe ASIC wafer is fabricated, and TSVs and a two-layer backside RDL are formed.
  • Bondμbumps are formed by plating, and CdTe is flip-chip bonded (CoW).
  • Dicing & testingModules are separated by laser dicing and tested using electrode probing, test pulses and X-rays.
  • TilingModules are tiled and bump-bonded onto a PCB (FR4, etc.), and the panel is tested with X-rays.

→ See the product made with this process (CdTe PhotonCounting FPD)

*As an alternative route, room-temperature stacking by conductive paste printing followed by tiling onto a Si interposer is also supported.

04 / PROCESS

Case Study: 3D-CMOS

Overview of how 3D-CMOS is made (photodiodes and readout ASICs are made separately, then bonded and arranged)

The PD side and ASIC side use different foundries and processes. Neither imposes its constraints on the other until bonding.

  • Build separatelyPhotodiodes and readout ASICs are each made with a process suited to them.
  • BondKnown-good dies are flip-chip bonded to each other.
  • ArrangeThe bonded chips are arranged to form a panel.

→ See the product made with this process (3D CMOS FPD)

Consult on Contract Chiplet Development

Consult with us individually on the design, assembly and manufacturing of heterogeneous bonding involving compound semiconductors.

Request a technical consultation

ANSeeN Inc. / TEL: 053-522-7708 / Contact: https://anseen.com/contact/

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