CHIPLET / PD DEVICE

PD Device Design & PrototypingConsultation basis

We adapt how we build detector elements to each material. Whatever the material, we design around the electrode layout and pitch of the ASIC it will be bonded to, and advance prototyping while verifying through both simulation and measurement.

Request a technical consultation Back to Chiplet

PHOTO

Simulation Example

How the depletion region expands within a pixel as reverse bias increases (2D device simulation).

CASES

Case Studies

Direct-conversion CdTe and an SOI photodiode with a partitioned scintillator: two types of detector elements designed for our own Imaging products.

Junction formation by laser doping (conceptual diagram)

CASE · CdTe

pn-type CdTe detector element

MethodDirect conversion (X-ray → charge)
JunctionLow-temperature pn junction formed in CdTe crystal by laser doping. Electrodes and junctions are processed in-house
Key featureCaptures the energy of each photon one by one, enabling material discrimination (color X-ray)

A backside hole array confines scintillator light within each pixel

CASE · 3D-CMOS

SOI photodiode + partitioned scintillator

PhotodetectionPhotodiodes fabricated with a foundry SOI process
IsolationA ring around each pixel electrically isolates adjacent pixels
PartitionsA hole array is etched into the substrate backside by TSV etching and filled with GOS (industrial) or CsI (medical). Together with the ring, this suppresses optical crosstalk

SPECIFICATIONS

Scope

Materials	Si / CdTe / TlBr, etc.
Method	Direct conversion (CdTe, etc.) / SOI photodiode + partitioned scintillator (Si)
Junction formation	Low-temperature, low-pressure laser doping (compound semiconductors) / Foundry SOI process (Si)
Design scope	Pixel structure, electrode layout and pitch (designed for bonding to the ASIC)
Evaluation	2D device simulation, measurement of test elements and prototypes, and comparison of the two
Status	Consultation basis

SIMULATION

Device Design Simulation

We solve the pixel cross-section in 2D to estimate, before prototyping, how the depletion layer expands with bias and what happens between neighboring pixels and the readout circuit.

*The simulation figures shown were created for the website to illustrate our methods. They do not contain values from actual products or prototypes.

Potential & depletion2D and axisymmetric solutions of the Poisson equation visualize depletion expansion and punch-through versus bias, to define the operating bias range.
Breakdown voltageBreakdown voltage is predicted with ionization integrals, and field concentration at pixel corners is evaluated with an axisymmetric model.
CapacitanceJunction depletion capacitance and wiring parasitic capacitance are estimated and checked against readout circuit specifications.
Collection efficiency & time responseDrift-diffusion calculations with concentration-dependent mobility and lifetime predict how much generated charge is collected, and how quickly.
CrosstalkMinority carrier diffusion is solved to evaluate how the depth of isolation structures affects leakage into neighboring pixels.

MEASUREMENT

Prototype Measurement and Comparison with Simulation

Simulation assumptions are re-derived from real devices. We measure prototypes and test elements, and wherever results disagree with simulation, we isolate the cause until it is understood.

Structure extraction from design dataLayout data is read directly to confirm the actual pixel structure and junction area from layers, hierarchy and dimensions.
Measured doping profilesDepth profiles obtained by spreading resistance measurement are imported directly into the simulation model.
Test element evaluationSheet resistance, diode characteristics and breakdown voltage are measured and compared with doping profile calculations to estimate layer shapes and diffusion lengths.
Dark-field area evaluationDark output of each pixel is separated into an offset component and a component proportional to exposure time, and dark current distribution is evaluated across the area for each bias. Dark current components are separated by calculation to identify their sources.
Analysis with packaging in mindWafer warpage after thinning and stacking is predicted with laminated plate theory and compared with measurements, and stress concentrated at backside holes and during bonding is estimated. Periodic patterns appearing in images are also compared with structure-based predictions to narrow down their cause.

→ See the full bonding and packaging process (Chiplet)

ANSeeN Inc. / TEL: 053-522-7708 / Contact: https://anseen.com/contact/