3D CMOS FPDIn development
A 3D CMOS X-ray image sensor that optimizes the photodetector and signal-processing circuitry as separate chips in separate processes, then stacks them. Per-pixel walls confine scintillator light, preserving contrast down to fine structures.
Product Photos
*Development unit mounted on an evaluation board.
Specifications
| Name | 3D CMOS FPD |
|---|---|
| Detection method | Scintillator + 3D stacked CMOS (indirect conversion) |
| Sensor thickness | 300μm |
| Active imaging area | Approx. 205 x 205 mm |
| Pixel count | 2048 x 2048 pixels |
| Pixel pitch | 100μm |
| Resolution | 4.23 lp/mm (MTF 50%) |
| Maximum frame rate | 150 fps |
| Bit depth | 14 bit |
| Minimum detectable energy | — |
| Operating modes | Low-gain mode / High-gain mode |
| Shutter type | Global shutter |
| Interface | Camera Link x 2 / GbE (GbE has operating speed limitations) |
| Power supply | 24V DC |
| External dimensions | — |
| Weight | — |
| Operating temperature | 40℃ or below (non-condensing) |
Technical Details
Optimized separately, then stacked
The photodetector (photodiode) and the signal-processing ASIC call for entirely different optimal materials and processes. Each is fabricated in a dedicated process, and the two are joined into a single sensor by flip-chip bonding. Wiring is routed through an RDL (redistribution layer), and no TSVs are used for electrical connections. The scintillator is chosen to suit the application: GOS (industrial and non-destructive testing) or CsI (medical).
Suppressing optical crosstalk with a walled structure
A hole array etched into the back of the substrate is filled with scintillator, forming walls around each pixel. Combined with a peripheral ring structure, this virtually eliminates light leaking into neighboring pixels.
Contrast maintained at high frequencies
Because the walls limit the spread of light, contrast holds up even at the high spatial frequencies that correspond to fine structures. Measured under RQA5 conditions, the spatial frequency at which MTF reaches 50% is 4.23 lp/mm, far exceeding conventional TFT (1.60 lp/mm) and CMOS (1.24 lp/mm) designs in which the scintillator is applied as a uniform sheet.
ANSeeN Inc. / TEL: 053-522-7708 / Contact: https://anseen.com/contact/