We design readout circuits by working backward from the constraints of the detector and its assembly. The circuit and layout are decided with everything taken into account: whether to count photons or integrate charge, what pitch to bond at, and how the chips will be tiled.
Pixel design is defined end to end: from the overall chip architecture, to blocks (the repeating unit of pixels), down to the layout of circuit elements within a single pixel.
Two types of ASICs designed for our own Imaging products.
Daisy-chain connection passing data to the adjacent module
Single pixel → 32×32 block → ASIC with 256×256 pixels → 4×4 tiles for 1024×1024 pixels
| Circuit architecture | Photon counting (counts photons one by one and discriminates them by energy) / charge-integrating (CTIA) |
|---|---|
| Structure | Hybrid structure bonded to the detector (TSV-based) |
| Pitch conversion | RDL (redistribution layer) matches the electrode pitch of the bonding counterpart |
| Backside readout | TSVs route signals to the backside, allowing tiling with all four sides butted together |
| Manufacturing | Circuit and layout finalized with a design partner, wafers fabricated at a foundry. Known-good dies selected by die sort testing |
| Status | Individual consultation |
Depending on the characteristics of the detector, we choose either photon counting, which counts photons one by one, or the integrating type (CTIA), which accumulates and reads out charge. In the integrating type, the reset level and signal level are stored separately and subtracted to cancel pixel-to-pixel variation.
We read layout data directly to verify the hierarchy and wiring connectivity. PD device analysis results feed into the pixel circuit design, allowing us to estimate noise all the way to the bonded assembly.
*The figures shown were created for the web to illustrate our methods. They do not contain circuits or data from actual products or prototypes.
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